The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a switching circuit for switching voltage to be supplied to a decoder which is used for selecting memory cell gate.
In the conventional semiconductor integrated circuit, a switching circuit is provided for switching a voltage to be supplied to a decoder for selecting gate of he memory cell, so as to supply an appropriate voltage to the decoder of the gate.
One of the conventional switching circuits is disclosed in Japanese patent publication No. 6-103426, Japanese patent No. 2516296 and Japanese laid-open patent publication No. 10-505953. Japanese patent publication No. 6-103426 discloses that a direct current between a power source and a ground is prevented to reduce a power consumption of a driver circuit of a liquid crystal display device. Japanese patent No. 2516296 discloses that in a word line driver circuit of a dynamic random access memory, a gate of an access transistor is kept in negative potential for driving word lines. Japanese laid-open patent publication No. 10-505953 discloses that in a control circuit of a thyristor, an igniter gate is provided to switch the thyristor into conductive state for application of a positive voltage to the gate of the thyristor.
FIG. 1 is a circuit diagram illustrative of one of the conventional switching circuits. The circuit comprises a series connection of two switching transistors M1 and M2 such as MOS field effect transistors between first and second voltage supply lines L1 and L2. The first switching transistor M1 has a gate which receives a first gate control signal S1. The second switching transistor M2 has a gate which receives a second gate control signal S2. A source of the first switching transistor M1 is connected to an output node OUT. A source of the second switching transistor M2 is connected to the second voltage supply line L2. The first voltage supply line L1 supplies a higher voltage than the second voltage supply line L2. For example, the first voltage supply line L1 supplies a positive voltage level Vdd and the second voltage supply line L2 supplies a ground voltage level Vss. Alternatively, the first voltage supply line L1 may supply a ground voltage level Vss and the second voltage supply line L2 may supply a negative voltage level Vneg. The first switching transistor M1 has a sub-gate which is connected to the second voltage supply line L2. The second switching transistor M2 also has a sub-gate which is connected to the second voltage supply line L2. Thus, both the sub-gates of the first and second switching transistors M1 and M2 are commonly connected to the second voltage supply line L2. The above first and second switching control signals S1 and S2 are supplied to control the voltage level appearing at the output node OUT. Each of the first and second switching control signals S1 and S2 may be the power voltage level Vcc, the ground voltage level Vss and the negative voltage level Vneg.
The following descriptions will be in the case when the positive voltage Vdd appears at the output node OUT. The first gate control signal S1 is the power voltage Vcc, whilst the second gate control signal S2 is either the ground voltage Vss or the negative voltage Vneg. The first voltage supply line L1 supplies the positive voltage Vdd so that a drain of the first switching transistor M1 receives the positive voltage Vdd. The second voltage supply line L2 supplies either the ground voltage Vss or the negative voltage Vneg so that a source of the second switching transistor M2 receives either the ground voltage Vss or the negative voltage Vneg. A maximum output voltage level appearing at the output node OUT is a voltage corresponding to subtraction of a threshold voltage of the first switching transistor M1 from the power voltage Vcc, for example, (Vccxe2x88x92Vtm1). If Vdd is lower than Vccxe2x88x92Vtm1, then Vdd appears on the output node OUT.
The first threshold voltage Vtm1 of the first switching transistor M1 receives an influence of a back gate bias characteristic due to a second threshold voltage Vtm2 of the second switching transistor M2 since a source voltage of the first switching transistor M1 is higher in potential than the sub-gate voltage level of the first switching transistor M1 by the second threshold voltage Vtm2 of the second switching transistor M2. For this reason, if the power voltage level Vcc is low, then the positive voltage Vdd does not appear on the output node OUT.
In the above circumstances, it had been required to develop a novel switching circuit free from the above problem.
Accordingly, it is an object of the present invention to provide a novel switching circuit free from the above problems.
It is a further object of the present invention to provide a novel switching circuit capable of outputting a predetermined voltage level onto an output node even if a power voltage level is low.
It is a still further object of the present invention to provide a novel switching circuit capable of preventing the switching circuit from performing bipolar action or thyristor action.
The present invention provides a circuitry comprising: a first switching transistor connected in series between an output node and a first voltage supply line which supplies a first voltage level, the first switching transistor having a first control gate receiving a first control signal; and a second switching transistor connected in series between the output node and a second voltage supply line which supplies a second voltage level which is lower than the first voltage level, the second switching transistor having a second control gate receiving a second control signal, so that the first and second switching transistors are connected in series between the first and second voltage supply lines, wherein the first switching transistor has a first sub-gate which is connected to the output node, and the second switching transistor has a second sub-gate which is connected to the second voltage supply line.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.